The invention relates to vertical bipolar transistors, especially those integrated in high-frequency and very large-scale integration (VLSI) technologies. More particularly, the invention relates to the characteristics and the production of the emitters of such transistors.
In bipolar technologies using a polysilicon emitter, the emitter is formed by depositing polysilicon (which may be carried out in a conventional oven) followed by doping. Alternatively, the emitter may be doped in situ in a chemical vapor deposition (CVD) reactor. In both cases, an oxide layer is present at the emitter/base interface. This layer limits the hole current in the base as the injected electrons continue to flow because of the tunnel effect. This contributes to achieving a sufficient current gain (Ic/Ib).
However, such transistors with a polysilicon emitter exhibit low-frequency noise manifested in low-frequency fluctuations in the transistor current. This is particularly problematic in the case of radio frequency (RF) circuits which incorporate such transistors for separating two close carriers. This may also be problematic in the case of oscillators.
An object of the invention is to provide a vertical bipolar transistor having reduced low-frequency noise while at the same time having acceptable static parameters and a correct current gain.
According to the invention, a process for fabricating a vertical bipolar transistor includes producing an intrinsic collector, for example by epitaxy or implantation, on an extrinsic collector layer buried in a semiconductor substrate. The method also includes producing a lateral isolating region surrounding the upper part of the intrinsic collector and of an offset extrinsic collector well. Moreover, a base (e.g., a completely silicon base or preferably a base with an silicon-germanium (SiGe) heterojunction) is produced above the intrinsic collector and above the lateral isolating region.
The base may be formed by non-selective epitaxy of a semiconductor region and include at least one silicon layer (in the case of a completely silicon base). Furthermore, the method may include producing an in-situ doped emitter, which includes first and second substeps. The first substep includes producing a first emitter part from single-crystal silicon and in direct contact with a part (xe2x80x9cemitter windowxe2x80x9d) of the upper surface of the semiconductor region above the intrinsic collector. The second substep includes producing a second emitter part from polycrystalline silicon and separated from the single-crystal-silicon first emitter part by a separating oxide layer.
In other words, the emitter of the transistor according to the invention includes of two parts. A first part (i.e., a bottom part), which is close to the emitter-base junction is grown epitaxially. This makes it possible to move the oxide interface away from the junction, and is advantageous because the oxide interface is a source of low-frequency noise. Next, after having produced an oxide interface on the epitaxially grown single-crystal part, the emitter is produced from in-situ doped polysilicon. Thus, it is possible to maintain high static characteristics and a high current gain.
According to one method of implementing the invention compatible with a SiGe base, the step of producing the base includes non-selective epitaxy of a multilayer forming the semiconductor region. The multilayer may include, apart from the silicon layer, at least one silicon-germanium layer, e.g., a SiGe layer encapsulated by two silicon layers or a SiGe layer on a silicon layer. Moreover, the first substep of producing the emitter may include epitaxially growing silicon on a predetermined window (xe2x80x9cemitter windowxe2x80x9d) in the surface of the multilayer above the intrinsic collector to provide, above the window, the first part of the emitter region. The first part of the emitter region is formed from single-crystal silicon and in direct contact with the upper layer of the multilayer. Regarding the second substep, a separating oxide layer may be advantageously deposited on the first part of the emitter region, and polycrystalline silicon may be deposited on the separating oxide layer.
As indicated above, the production of a single-crystal partially epitaxially-grown emitter directly on the base (note that the emitter-base junction defining the upper part of the intrinsic base in fact lies in the upper encapsulation layer) results in there being no interface oxide near the emitter-base junction. As such, this leads to an appreciable reduction in the low-frequency noise. Furthermore, the presence of a base having a silicon-germanium heterojunction also contributes to an acceptable current gain because of the lowering of the potential barrier. The combination of a SiGe base and a emitter is therefore particularly advantageous from the current/gain standpoint.
The first substep of producing the emitter (i.e., the single-crystal part) may include first and second phases. The first phase may include depositing a first layer of silicon dioxide on the surface of the multilayer and depositing a second layer of silicon nitride on the first layer. The first substep may further include etching through the second layer to the first layer in a zone corresponding to the location of the emitter window. The zone may then be chemically deoxidized to provide in the window a silicon surface having an oxygen atom concentration of less than 1015 atoms/cm2.
The second phase of the first substep may include exposing the semiconductor block provided in the first phase to a silane/dopants gas mixture in a non-oxidizing controlled atmosphere. This may be done, for example, under vacuum in an ultra-clean chemical vapor deposition (CVD) reactor well known to those skilled in the art.
Thus, the invention makes it possible to use conventional conditions for depositing polysilicon in an ultra-clean CVD reactor. However, the silicon grows as a single crystal on the base because of the chemically clean nature of the window in the base. On the other hand, the use of conventional conditions for depositing polysilicon makes it possible in the second substep (i.e., the top part of the emitter) to obtain polycrystalline silicon because of the presence of the separating oxide layer.
After the second substep, a polycrystalline silicon layer is provided which may be etched to form an emitter having an upper region wider than the emitter window and extending on part of the silicon nitride layer. Isolating spacers in contact with the vertical walls of the wider upper region of the emitter may then be formed.
The first phase of the first substep may include depositing a thick third layer of silicon dioxide on the second layer of silicon nitride and preliminarily etching into the silicon dioxide third layer to the second layer in a region corresponding to the position of the zone. The region consequently corresponds to the emitter window. Thus, after the first phase, a semiconductor block is obtained which includes a multilayer of the three isolating layers defining a cavity of the same width as the emitter window.
After the second phase (i.e., after epitaxy of the emitter) and after the second substep, the cavity may be filled with the single-crystal silicon with the separating oxide layer thereon and the polycrystalline silicon on the separating oxide layer. The third layer of silicon dioxide is then etched on either side of the emitter block formed in the cavity, and isolating spacers in contact with the vertical walls of the emitter are formed.
In other words, according to this embodiment of the invention, a smaller distance is obtained between the edge of the emitter and the implanted zone of the extrinsic base. This helps to further decrease the base resistance as well as the base-collector capacitance. Furthermore, this reduced distance is controlled by a single level of photolithography.
According to another embodiment of the invention, a vertical bipolar transistor includes an intrinsic collector on an extrinsic collector layer buried in a semiconductor substrate, a lateral isolating region surrounding the upper part of the intrinsic collector, an offset extrinsic collector well, and a base. The base may include a semiconductor region located above the intrinsic collector and above the lateral isolating region and including at least one silicon layer. The transistor may also include a doped emitter, surrounded by the base, having a first part formed from single-crystal silicon and in direct contact with the upper surface of the semiconductor region in a predetermined window (emitter window) in the upper surface located above the intrinsic collector. The emitter may also have a second part formed from polycrystalline silicon. The two parts of the emitter may be separated by a separating oxide layer located some distance from the emitter-base junction of the transistor.
The window in the upper surface of the semiconductor region may advantageously have an oxygen atom concentration of less than about 1015 atoms/cm2, for example. The height of the first (single-crystal) part of the emitter may be between a few nanometres and a few tens of nanometres. If the base is a base having a silicon-germanium heterojunction, for example, the semiconductor region may be advantageously formed from a multilayer comprising at least one silicon layer and at least one SiGe layer.